Peripheral Components Interconnect (PCI) Express (hereinafter referred to as PCIe) is an interface standard of serial transfer, which has been formulated by the Peripheral Components Interconnect-Special Interest Group (PCI-SIG).
In the PCIe, conveyance of information between devices is performed by transferring a packet through a network that connects the devices to each other. A device that is a transmission source of a request packet, which is called a transaction layer packet (TLP) request, is called a requester, and a device that is a transmission destination of the TLP request is called a completer. When the requester does not receive a response packet, which is called a TLP completion, from the completer, within a certain time period, a completion timeout is detected in the requester.
A technology is known by which causes of some errors are identified in the PCIe. For example, for an error that occurs in a case of a TLP request that is not supported by the PCIe (that is, “unsupported request error”), the location that has caused the error (in this case, the requester) may be identified based on information that has been written into a header log register provided for a completer.
However, there is no related art in which identification of a cause of a completion timeout is focused on. The completion timeout is detected in the requester, but a log related to the completion timeout is not stored in the header log register. In addition, the completion timeout may be caused by a requester, a completer, or a link or the like on a path between the requester and the completer.
“PCI Express Base Specification Revision 3.0”, Peripheral Components Interconnect-Special Interest Group, Nov. 10, 2010, p. 151 is the related art.
Japanese Laid-open Patent Publication No. 2008-225694 is also the related art.